The present invention relates generally to integrated circuit fabrication, and more particularly, to a method for fabricating devices in core and periphery regions of a semiconductor substrate having narrow spacers while using disposable wide spacers for forming the drain and source of the device in the periphery region.
FIG. 1 shows a cross-sectional view of a first integrated circuit device which is a flash memory cell 102 formed within a core region 104 of a semiconductor substrate 106 and of a second integrated circuit device which is a high voltage field effect transistor 108 formed within a periphery region 110 of the semiconductor substrate 106. For example, the flash memory cell 102 may be part of an array of flash memory cells formed within a core region area of the semiconductor substrate 106, and the high voltage field effect transistor 108 may be part of an integrated circuit formed within a periphery region area of the semiconductor substrate 106 for supporting operation of the array of flash memory cells. Such flash memory devices are known to one of ordinary skill in the art of memory device fabrication.
For fabricating the flash memory cell 102, a flash memory cell gate stack 112 is formed on an active area of the semiconductor substrate 106 within the core region 104. The active area of the semiconductor substrate 106 within the core region 104 is defined by the surrounding shallow trench isolation structures 122 and 124. The flash memory cell gate stack 112 includes a tunnel dielectric 114, a floating gate 116, a control dielectric 118, and a control gate 120. Such a gate stack 112 for a flash memory cell is known to one of ordinary skill in the art of memory device fabrication.
In addition, a source bit line junction 134 and a drain bit line junction 136 are formed within the core region 104 of the semiconductor substrate 106 to the sides of the flash memory cell gate stack 112. The source and drain bit line junctions 134 and 136 are typically formed from implantation of a dopant into exposed portions of the core region 104 of the semiconductor substrate 106 after formation of the flash memory cell gate stack 112. An implantation mask would be formed over the periphery region 110 during such an implantation process for forming the source and drain bit line junctions 134 and 136. Such processes for forming the source and drain bit line junctions 134 and 136 of the flash memory cell 102 are known to one of ordinary skill in the art of memory device fabrication.
For fabricating the high voltage field effect transistor 108, a transistor gate stack 128 is formed on an active area of the semiconductor substrate 106 within the periphery region 110. The active area of the semiconductor substrate 106 within the periphery region 110 is defined by the surrounding shallow trench isolation structures 124 and 126. The transistor gate stack 128 includes a gate dielectric 130 and a transistor gate 132. Such a gate stack 128 for a high voltage field effect transistor is known to one of ordinary skill in the art of memory device fabrication. The thickness of the gate dielectric 130 is typically larger such that the field effect transistor 108 has a larger threshold voltage and a higher gate break-down voltage for the high voltage field effect transistor 108 that operates with higher bias voltages such as 9 Volts for example.
Referring to FIGS. 1 and 2, a dopant is implanted into exposed regions of the periphery region 110 of the semiconductor substrate 106 for forming LDD (lightly doped drain) regions 138 and 140 to the sides of the transistor gate stack 128. An implantation mask 137 is formed over the core region 104 of the semiconductor substrate 106 such that the LDD regions 138 and 140 are formed for the high voltage field effect transistor 108. The dopant may be an N-type dopant such as arsenic or may be P-type dopant such as boron. Implantation processes for formation of such LDD regions 138 and 140 are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIGS. 2 and 3, after formation of the LDD regions 138 and 140 for the high voltage field effect transistor 108, first spacers 142 are formed at the sidewalls of the flash memory cell gate stack 112, and second spacers 144 are formed at the sidewalls of the transistor gate stack 128. The first and second spacers 142 and 144 are comprised of a dielectric material such as silicon dioxide (SiO2) for example, and processes for formation of such spacers 142 and 144 are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIGS. 3 and 4, after formation of the first and second spacers 142 and 144, a dopant is implanted to form a drain junction 150 and a source junction 152 of the high voltage field effect transistor 108. An implantation mask 153 is formed over the core region 104 of the semiconductor substrate 106 such that the drain and source junctions 150 and 152 are formed for the high voltage field effect transistor 108. The dopant may be an N-type dopant such as arsenic or may be P-type dopant such as boron. Implantation processes for formation of such drain and source junctions 150 and 152 are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIGS. 4 and 5, a drain bit line silicide 156 is formed with the drain bit line junction 136 for providing contact to the drain bit line of the flash memory cell 102. In addition, a drain silicide 158 is formed with the drain junction 150 for providing contact to the drain of the high voltage field effect transistor, and a source silicide 160 is formed with the source junction 152 for providing contact to the source of the high voltage field effect transistor 108. Furthermore, a gate silicide 164 is formed with the transistor gate 132 for providing contact to the gate of the high voltage field effect transistor 108. Processes for forming such suicides 156, 158, 160, and 164 are known to one of ordinary skill in the art of integrated circuit fabrication.
A silicide is not shown to be formed with the source bit line junction 134 and the control gate 120 for the flash memory cell 102 in FIG. 5 because the source bit line junctions for the array of flash memory cells are coupled together and because the control gates for a row of flash memory cells are coupled together. Then, contacts are made to the coupled source bit line junctions and the coupled control gates outside of the active device area for the flash memory cell 102, as known to one of ordinary skill in the art of flash memory devices.
Referring to FIGS. 5 and 6, via structures 174, 176, 178, and 180 are formed through an inter-level dielectric layer 182 to the silicides 156, 158, 164, and 160, respectively, for providing connection between the flash memory cell 102 or the high voltage field effect transistor 108 to interconnect structures 188, 190, 192, and 194, respectively. Processes for formation of such via structures and such interconnect structures are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring back to FIG. 5, the spacers 142 and 144 are formed to have a spacer width 166. Given a predetermined width of the gate stacks 112 and 128 and given the active device area for fabricating the flash memory cell 102 and the field effect transistor 108, the width 166 of the spacers 142 and 144 limits the width 168 of the drain and source silicides 156, 158, and 160. If the width 166 of the spacers 142 and 144 is wider, then less space is available for forming the drain and source suicides 156, 158, and 160.
Referring to FIG. 7, during formation of the via structure 174, the via structure 174 may be misaligned to be shifted too much to the left toward the spacer 142. In that case, a portion of the via structure 174 is formed on the spacer 142 and a portion of the via structure 174 is formed on the drain bit line silicide 156. With such misalignment, the via structure 174 does not make full contact with the drain bit line silicide 156. Such partial contact of the via structure 174 with the drain bit line silicide 156 disadvantageously results in higher resistance contact to the drain bit line of the flash memory cell 102.
FIG. 8 illustrates another flash memory cell 195 formed next to the flash memory cell 102 in an array of flash memory cells fabricated in the core region 102 in conjunction with fabrication of the flash memory cell 102, as known to one of ordinary skill in the art of flash memory devices. Typically, the two adjacent flash memory cells 102 and 195 share the common drain bit line junction 136 having the drain bit line silicide 156 and the via structure 174 formed thereon, and have separate source bit line junctions 134 that are coupled together, as known to one of ordinary skill in the art of flash memory devices. Spacers 142 are formed concurrently at the sidewalls of the flash memory cell gate stacks of the flash memory cells 102 and 195.
Referring to FIGS. 5 and 8, if the width 166 of the spacers 142 is larger, less area is available for the drain bit line silicide 156 and the via structure 174 formed between the spacers 142. Referring to FIG. 9, during formation of the via structure 174, the via structure 174 may be misaligned to be shifted too much to the left toward the spacer 142 of the left flash memory cell 102. In that case, a portion of the via structure 174 is formed on the spacer 142 of the left flash memory cell 102 and a portion of the via structure 174 is formed on the drain bit line silicide 156. Alternatively, referring to FIG. 10, the via structure 174 may be misaligned to be shifted too much to the right toward the spacer 142 of the right flash memory cell 195. In that case, a portion of the via structure 174 is formed on the spacer 142 of the right flash memory cell 195 and a portion of the via structure 174 is formed on the drain bit line silicide 156. With such misalignment, the via structure 174 does not make full contact with the drain bit line silicide 156. Such partial contact of the via structure 174 with the drain bit line silicide 156 disadvantageously results in higher resistance contact to the drain bit line of the flash memory cells 102 and 195.
Thus, a narrower width of the spacers 142 is desired for maintaining full contact of the via structure 174 with the drain bit line silicide 156 even with misalignment of the via structure 174. On the other hand, referring to FIGS. 4 and 5, with a scaled down width 166 of the spacers 142 and 144, the distance between the drain and source junctions 150 and 152 to the sidewalls of the transistor gate 132 for the high voltage field effect transistor 108 is decreased. With such decreased distance between the drain and source junctions 150 and 152 to the sidewalls of the gate structure 132 for the high voltage field effect transistor 108, the gate break-down voltage of the high voltage field effect transistor 108 undesirably decreases.
Such decreased gate break-down voltage of the high voltage field effect transistor 108 resulting from the narrower spacers 142 and 144 may render the high voltage field effect transistor 108 inoperable at high voltages such as 9 Volts for example. Nevertheless, narrower spacers 142 and 144 are desired for enhancing full contact-of the via structure 174 to the drain bit line silicide 156 even with potential misalignment during formation of the via structure 174.
Thus, a narrow width 166 of the spacers 142 and 144 is desired while maintaining a high break-down voltage of the high voltage field effect transistor 108 in the periphery region 110.
Accordingly, in a general aspect of the present invention, wide disposable spacers are used for forming the drain and source junctions of the high voltage field effect transistor in the periphery region for maintaining a high break-down voltage of such a field effect transistor. In addition, narrow permanent spacers are formed for defining the wide width of the silicides formed for the flash memory cell formed in the core region and for the high voltage field effect transistor formed in the periphery region.
In one embodiment of the present invention, for fabricating a first device within a core region of a semiconductor substrate and a second device within a periphery region of the semiconductor substrate, a first gate stack is formed on the semiconductor substrate within the core region for the first device, and a second gate stack is formed on the semiconductor substrate within the periphery region for the second device. A liner layer of a first dielectric material is deposited on any exposed surface of the semiconductor substrate, the first gate stack, and the second gate stack, and a liner layer of a second dielectric material is deposited on the liner layer of the first dielectric material.
In addition, disposable spacers comprised of the first dielectric material are formed on the liner layer of the second dielectric material at sidewalls of the first gate stack and at sidewalls of the second gate stack, and the disposable spacers are formed to have a first width; An implantation mask is patterned to remain over the core region of the semiconductor substrate. A drain junction and a source junction of the second device are formed by implanting a dopant into the periphery region of the semiconductor substrate to the sides of the disposable spacers of the second gate stack. The implantation mask is then removed from the core region of the semiconductor substrate.
Furthermore, the disposable spacers are etched away from the first gate stack and the second gate stack, and the liner layer of the second dielectric material is not etched away during etching away of the disposable spacers. Permanent spacers comprised of the second dielectric material are formed on the liner layer of the second dielectric material at sidewalls of the first gate stack and at sidewalls of the second gate stack. The permanent spacers are formed to have a second width that is less than the first width of the disposable spacers.
In an example embodiment of the present invention, the first device formed in the core region is a flash memory cell, and the first gate stack is comprised of a tunnel dielectric, a floating gate, a control dielectric, and a control gate. In addition, the second device formed in the periphery region is a high voltage field effect transistor, and the second gate stack is comprised of a gate dielectric and a transistor gate.
In this manner, the drain and source junctions of the high voltage field effect transistor formed in the periphery region are formed to be spaced wider apart with use of the wider disposable spacers. Such wider spaced drain and source junctions maintain a higher break-down voltage of the high voltage field effect transistor formed in the periphery region. Furthermore, the disposable spacers are etched away, and narrower permanent spacers are formed on the sidewalls of the gate stacks for advantageously defining a wider width of the silicides to be formed in the drain and source junctions of the devices.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.